(a) Field of the Invention
The present invention relates to a power source for generating positive and negative voltage sources and, more particularly to the control of a power source circuit which generates a voltage source having a polarity inverse to the polarity of the source voltage supplied to the semiconductor device.
(b) Description of the Related Art
Flash memories are increasingly used as nonvolatile memory devices for storing programs and data. In programming or erasing a memory cell in a flash memory, a potential difference as high as 16 to 18 volts is generally applied between the source and the control gate of the memory cell.
Until recently, only a positive voltage source is generally used in the flash memory, wherein the control gate is applied with 16 to 18 volts while maintaining the source potential of the memory transistor at zero volt. In this case, the circuit line connected to the control gate must have a withstand voltage of 16 to 18 volts, which results in a large chip size due to a large element dimension for obtaining a large withstand voltage.
Recently, a negative voltage source is also used in a flash memory to reduce the potential of the positive voltage source applied to the control gate. For example, if the source voltage is -4 volts, 12 volts is sufficient for the control gate voltage to obtain a voltage difference of 16 volts. This remarkably reduces the withstand voltage of the control gate as well as the control circuit for the control gate, thereby reducing the element dimensions and the chip size of the flash memory. For this reason, a negative voltage source is generally required in the semiconductor device having a flash memory.
FIGS. 1A and 1B show the voltages applied for programming and erasing, respectively, a memory cell in a flash memory by using a known Fowler-Nordheim (F-N) tunneling effect. In the programming, electrons are withdrawn from the floating gate by applying -9 volts to the control gate and 6 volts to the source electrode, whereas in the erasing, electrons are injected into the floating gate by applying 12 volts to the control gate and -4 volts to the source electrode and the well receiving therein the memory cell.
If the negative voltage -9 volts or -4 volts fluctuates due to the unstable characteristics of the negative voltage source, the amount of electrons injected or withdrawn into/from the floating gate varies with the fluctuation of the negative voltage. For example, if the applied voltage is above -4 volts, the amount of injected electrons is less than the designed amount, which results in an eventual programmed state shifting from the erased state in the memory cell due to the leakage of the electrons with the lapse of time. This defect must be avoided in the flash memory to prevent the erroneous data from occurring by stabilizing the negative voltage source in the semiconductor device.
Patent Publication JP-A-7-231647 proposes a power source circuit used in a flash memory, such as shown in FIG. 2. The power source circuit includes a positive source section 14A for generating a positive voltage source and a negative source section 13A for generating a negative voltage source. The positive source section 14A has a charge pump 17 and a comparator CP2 for comparing the output of a voltage divider 19A, which includes capacitors C3 and C4 for dividing the output potential of the charge pump 17, against a reference voltage Vref2 for a feed-back control of the charge pump 17. The positive source section 14A generates a positive voltage of 12 volts, for example.
The negative source section 13A has a control unit 10, a charge pump 11 and a voltage divider 12A including serial capacitors C1 and C2. The control unit 10 has a comparator CP1 for comparing the output of the voltage divider 12A dividing the voltage difference between the output of the charge pump 17 and the output of the charge pump 11 against a reference voltage Vref1. The capacitances of the capacitors C1 and C2 are designed such that the output of the voltage divider 12A is positive.
If the output voltage of the voltage divider 12A is higher than the reference voltage Vref1, the charge pump 11 is activated to lower the output voltage of the charge pump 11, whereas if the output of the voltage divider 12A is lower than the reference voltage Vref1, the charge pump 11 is inactivated to stop the lowering of the output voltage thereof.
By the operations as described above, the output voltage NVpp of the negative source section 13A is clumped at a constant negative voltage NVpp for use in programming or erasing memory cells in a flash memory.
In the power source circuit of FIG. 2, the output voltage NVpp of the negative source section 13A is controlled by feedback of the output of the voltage divider 12A. In the feedback loop, the output voltage of the positive source section 14A is unstable until a considerable length of time elapses since the supplied power source is turned on for the power source circuit. Since the negative source section 13A starts before the output of the positive source section 12A becomes stable, in the transient period after the power source is turned on, both the outputs of the positive source section 14A and the negative circuit section 13A are unstable. This prolongs the time length for stabilizing by which the power source circuit generates a stable negative output voltage NVpp.
Further, if a large number of memory cells are selected in an erasing operation of the flash memory, a large current flows through the output terminal OUT of the power source circuit to the memory cells, resulting in fluctuation of the negative output voltage NVpp. Although the fluctuation may be suppressed by the comparator CP1 after a considerable length of time, the fluctuation of the negative output voltage NVpp is transferred during a transient state to the output of the positive source section 14A through the voltage divider 12A, the output of which is also transferred to the non-inverting input of the comparator CP2 and to the input of the charge pump 17. The voltage fluctuations thus transferred further prolong the time length for stabilizing the negative output voltage NVpp.